1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and activation method of the same.
More particularly, the present invention relates to a semiconductor integrated circuit and activation method of the same for providing reduced power consumption by cutting off a transistor leak current.
2. Description of the Related Art
The MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technology is known to be able to provide reduced power consumption of the CMOS integrated circuit while preventing the reduction in operating speed of the MOS transistor (refer, for example, to Japanese Patent Laid-Open No. Hei 6-29834).
In a logic circuit block configuration using the MTCMOS technology, a virtual reference voltage line is provided. The virtual reference voltage line is connected to a reference voltage line via a switching transistor. A logic circuit block is connected between the virtual reference voltage line and a source voltage line.
A high-level voltage (e.g., source voltage) is applied to the source voltage line from an external system power supply of the CMOS integrated circuit or other power supply via a power pad. On the other hand, a low-level voltage (e.g., ground potential) is applied to the reference voltage line from an external system power supply of the CMOS integrated circuit or other power supply via a power pad.
In the logic circuit block using the MTCMOS technology, the switching transistor is on when the circuit block is active and off when the circuit block is inactive.
The n-type MOS transistor used as a switching transistor has a higher threshold voltage than the MOS transistor in the logic circuit block.
Therefore, when the logic circuit block is inactive, the leak current of the MOS transistor in the same circuit block is cut off by the switching transistor. On the other hand, when the logic circuit block is active, the MOS transistor in the same circuit block operates at high speed.
A logic circuit block configured as described above will be hereinafter referred to as a “footer-type MTCMOS logic circuit block.”
There is also a header-type MTCMOS logic circuit block which stands in contrast to a footer-type MTCMOS logic circuit block. In a header-type MTCMOS logic circuit block, a virtual source voltage line is provided. The virtual source voltage line is connected to a source voltage line via a switching transistor. A logic circuit block is connected between the virtual source voltage line and a reference voltage line.
The p-type MOS transistor used as a switching transistor has a higher threshold voltage than the MOS transistor in the logic circuit block.
In another logic circuit block configuration using the MTCMOS technology, a virtual source voltage line and virtual reference voltage line are provided. The virtual reference voltage line is connected to a reference voltage line via a switching transistor. The virtual source voltage line is connected to a source voltage line via another switching transistor. A logic circuit block is connected between the virtual source voltage line and virtual reference voltage line.
The p-type and n-type MOS transistors used as switching transistors have a higher threshold voltage than the MOS transistor in the logic circuit block.
There are cases in which two logic circuit blocks using the MTCMOS technology, one inactive and another active, coexist at the same time in a CMOS integrated circuit using the MTCMOS technology. Further, some logic circuit blocks not using the MTCMOS technology are connected directly to the source voltage line and reference voltage line and remain active at all times.
If the switching transistor which has been cutting off the leak current is turned on to operate (activate) the inactive logic circuit block, a sporadic current (hereinafter referred to as a “rush current”) will flow temporarily in a transient state (at activation) from an inactive to active state. It is known that this leads to a voltage change between the source voltage line and reference voltage line and eventually results in reduced operating speed and malfunction of other active logic circuit blocks.
To prevent malfunction of other logic circuit blocks, the switching transistor size and gate voltage are adjusted so that the peak of the rush current is suppressed.